Explore the intricacies of estimating propagation and contamination delays in 3-Nand gates for various sizes in this 36-minute lecture. Delve into the concepts of effort delay and parasitic delay while focusing on characterizing the delay of NOR gates. Gain valuable insights into digital circuit analysis and performance optimization techniques presented by NPTEL-NOC IITM.
Characterizing Delay of NOR Gate - Lecture 4.5
Overview
Syllabus
4.5 - Characterizing Delay of NOR gate
Taught by
NPTEL-NOC IITM
Related Courses
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Logical Effort and Parasitic Delay in NAND and NOR Gates - Lecture 4.7
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Introduction to Delay in CMOS - Lecture 3.5
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Extracting Capacitances of 3-NAND Gate for Delay Estimation - Lecture 4.4
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Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
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Skewed Gates and Best P/N Ratio - Lecture 6.5
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Optimizing Gate Size for Single-Path Digital Design - Lecture 5.4
