Explore the concepts of logical effort and parasitic delay in NAND and NOR gates through this 33-minute lecture. Derive the expressions for these crucial parameters, gaining a deeper understanding of their impact on digital circuit design and performance optimization.
Logical Effort and Parasitic Delay in NAND and NOR Gates - Lecture 4.7
Overview
Syllabus
4.7 - Logical effort and Parasitic delay
Taught by
NPTEL-NOC IITM
