Learn how to estimate logical effort and normalized parasitic delay for a 2-NOR gate in this 26-minute lecture. Explore the application of the Elmore delay method to determine the optimal P/N ratio. Gain insights into a general expression for calculating the best P/N ratio applicable to any gate design. Delve into the concept of skewed gates and their impact on circuit performance.
Skewed Gates and Best P/N Ratio - Lecture 6.5
Overview
Syllabus
6.5 - Skewed gates and best P/N ratio
Taught by
NPTEL-NOC IITM
Related Courses
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Logical Effort and Parasitic Delay in NAND and NOR Gates - Lecture 4.7
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Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
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Characterizing Delay of NOR Gate - Lecture 4.5
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Asymmetric Gates Analysis Using Short-Channel Current Model - Lecture 6.3
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Optimizing Gate Size for Single-Path Digital Design - Lecture 5.4
