Explore delay estimation techniques for various logic gates, including tristate inverters and multiplexers, in this 39-minute lecture from NPTEL-NOC IITM. Delve into the concepts of logical effort and parasitic delay, gaining valuable insights into their impact on different gate structures and circuit performance.
Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
Overview
Syllabus
5.1 - Logical effort and Parasitic delay for different gates
Taught by
NPTEL-NOC IITM
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