Explore the fundamental concepts of delay in CMOS circuits in this 27-minute lecture from NPTEL-NOC IITM. Delve into two critical delay parameters: propagation and contamination delay for digital circuits. Gain insights into realizing parasitic capacitances and input capacitances for accurate delay estimation. Examine the distinctions between falling and rising propagation delays, enhancing your understanding of CMOS circuit behavior and performance analysis.
Overview
Syllabus
3.5 - Introduction to Delay in CMOS
Taught by
NPTEL-NOC IITM
Related Courses
-
Design and Analysis of VLSI Subsystems
-
Digital Integrated Circuit Analysis and Design
-
Characterizing Delay of NOR Gate - Lecture 4.5
-
VLSI Chip Design and Simulation with Electric VLSI EDA Tool
-
Elmore Delay in Digital CMOS Circuits - Lecture 4.2
-
Logical Effort and Parasitic Delay for Different Gates - Lecture 5.1
