Explore a 14-minute technical presentation from Samsung's Yan Li that delves into advanced packaging technologies and their critical role in chiplet-based design for AI and HPC applications. Learn about the challenges facing Moore's Law and how heterogeneous integration offers a promising solution for boosting IC performance. Discover Samsung Semiconductor's recent innovations in packaging technologies, including developments in IP cores, Die to Die interface protocols, and Known Good Die solutions. Gain insights into emerging technologies like hybrid copper bonding and photonic integration that aim to enhance energy efficiency and memory bandwidth. Understand the ongoing efforts required to develop a robust chiplet ecosystem and the importance of advanced IC packaging in meeting future computing demands.
Advanced Packaging Technologies for Chiplet Adoption and Memory Integration in HPC and AI Applications
Open Compute Project via YouTube
Overview
Syllabus
AI/HPC: Advanced package tech. for chiplet adoption and memory integration in HPC/AI applications
Taught by
Open Compute Project
Related Courses
-
The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration
-
3D IC Test Strategy and DFT Methodologies for Advanced Packaging Technologies
-
Heterogeneous Integration and Chiplet Manufacturing in the US - A Technical Overview
-
Silicon Photonics Chiplet Package - Optical Assembly and Integration Technologies
-
Getting Moore with Less - How Chiplets and Open Interconnect Accelerate Cloud-Optimized AI Silicon
