Explore the evolution beyond Moore's Law in this technical presentation that delves into the challenges and opportunities of 3D heterogeneous integration (3DHI) in semiconductor design. Learn why traditional scaling approaches are becoming less economically viable for many semiconductor companies, with factors like reticle limits, yield issues, and astronomical design costs at advanced nodes pushing the industry toward new solutions. Discover how multi-chiplet 3D packaging and More-than-Moore architectures are emerging as alternatives to monolithic designs, offering innovative paths for microelectronics advancement. Examine the complex ecosystem challenges in transitioning from traditional system-on-chip (SoC) to system-in-package (SiP) approaches, including the critical role of EDA tools and design flows in enabling 3DHI implementation. Gain insights into silicon stacking technologies, packaging paradigms, and the convergence of IC and systems design requirements while understanding the technical and practical considerations for engineering teams moving from monolithic to heterogeneous integrated solutions.
The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration
Overview
Syllabus
Intro
Outline
Simply Following Moore's Law Alone is No Longer the Best Technical and Economical Path Forward
SIP/MCM vs. Heterogeneously Integrated Chiplet-Based Architectures The transition from system on a chip (SoC) to system in a package (SIP)
Heterogenous Integration Leverages Multiple Packaging Technologies
The Needs of IC and Systems Designers are Converging
Silicon Stacking The Next IC Packaging Paradigm Change is Here...
3D Packaging Versus Silicon Stacking (3DHI)
Multi-Chiplet 3D Flow Challenges
Top-Level Design Aggregation and Optimization
Standards and Co-Design Support
Monolithic Die Design To Silicon Stacking Implementation
Conclusion
Taught by
MEPTEC
