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NPTEL

Digital VLSI Testing

NPTEL and Indian Institute of Technology, Kharagpur via YouTube

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Overview

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PRE-REQUISITES: Digital Design / Digital Logic

INTENDED AUDIENCE: CSE, ECE, EE

INDUSTRIES APPLICABLE TO: Companies involved in the development of VLSI chips

COURSE OUTLINE: Testing is an integral part of the VLSI design cycle. With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging. Testing occupies 60-80% time of the design process. A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing. Design for testability (DFT) is a matured domain now and thus needs to be followed by all the VLSI designers. In this context, the course attempts to expose the students and practitioners to the most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in large quantities.

Syllabus

Lecture 1: Introduction.
Lecture 2: Introduction (Contd.).
Lecture 3: Introduction (Contd.).
Lecture 4: Introduction (Contd.).
Lecture 5: DFT.
Lecture 6: DFT (Contd.).
Lecture 7: DFT (Contd.).
Lecture 8: DFT (Contd.).
Lecture 9: DFT (Contd.).
Lecture 10:DFT (Contd.).
Lecture 11: Logic and Fault Simulation.
Lecture 12: Logic and Fault Simulation (Contd.).
Lecture 13: Logic and Fault Simulation (Contd.).
Lecture 14: Logic and Fault Simulation (Contd.).
Lecture 15: Logic and Fault Simulation (Contd.).
Lecture 16: Logic and Fault Simulation (Contd.).
Lecture 17: Test Generation.
Lecture 18: Test Generation (Contd.).
Lecture 19: Test Generation (Contd.).
Lecture 20: Test Generation (Contd.).
Lecture 21: Test Generation (Contd.).
Lecture 22: Test Generation (Contd.).
Lecture 23: Test Generation (Contd.).
Lecture 24: Logic BIST.
Lecture 25: Logic BIST (Contd.).
Lecture 26: Logic BIST (Contd.).
Lecture 27: Logic BIST (Contd.).
Lecture 28: Test Compression.
Lecture 29: Test Compression (Contd.).
Lecture 30: Test Compression (Contd.).
Lecture 31: Test Compression (Contd.).
Lecture 32: Low Power Testing.
Lecture 33: Low Power Testing (Contd.).
Lecture 34: Low Power Testing (Contd.).
Lecture 35: Low Power Testing (Contd.).
Lecture 36: Low Power Testing (Contd.).
Lecture 37 : Thermal Aware Testing.
Lecture 38 : Thermal Aware Testing (Contd.).
Lecture 39 : Thermal Aware Testing (Contd.).
Lecture 40 : Boundary Scan.
Lecture 41 : Boundary Scan (Contd.).
Lecture 42 : Boundary Scan (Contd.).
Lecture 43 : Boundary Scan (Contd.).
Lecture 44 : Boundary Scan (Contd.).
Lecture 45 : System/Network - On - Chip Test.
Lecture 46 : System/Network - On - Chip Test (Contd.).
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Digital VLSI Testing

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Reviews

4.2 rating, based on 4 Class Central reviews

Start your review of Digital VLSI Testing

  • Profile image for Jayanth Murala
    Jayanth Murala
    good course i have learned lot of things about digital vlsi testing form this course it is very helpful to everyone who are willing to learn the digital vlsi testing cource
  • Profile image for Shiksha Dwivedi
    Shiksha Dwivedi
    This was really an amazing course of nptel which help out us from ground to extreme knowledge regarding vlsi testing. Thank you so much. I'm very grateful to nptel.
  • ABRAR ALI MOHAMMED
    Good option
    We can open directly in YouTube
    Very great explanation
    Don't try to Skip watch every explanation
    Very usefull for upskillment purpose
  • Sakshi Kolure
    A great experience to learn about VLSI digital designing. This is helpful for me to know a better perspective about VLSI engineering. It is a new field for me. Although this course give to understanding ability to getting the practice and better known about real world.
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