The course will introduce the participants to the basic design flow in VLSI physical design automation, the basic data structures and algorithms used for implementing the same. The course will also provide examples and assignments to help the participants to understand the concepts involved, and appreciate the main challenges therein.INTENDED AUDIENCE : Computer Science and Engineering / Electronics and Communication Engineering / Electrical EngineeringPREREQUISITES : Basic concepts in digital circuit designINDUSTRY SUPPORT : Intel, Cadence, Mentor Graphics, Synopsys, Xilinx
Overview
Syllabus
Week 1 : Introduction to physical design automationWeek 2 : Partitioning, Floorplanning and PlacementWeek 3 : Grid Routing and Global RoutingWeek 4 : Detailed Routing and Clock DesignWeek 5 : Clock Routing and Power/GroundWeek 6 : Static Timing Analysis and Timing ClosureWeek 7 : Physical Synthesis and Performance Driven Design FlowWeek 8 : Interconnect Modeling and Layout CompactionWeek 9 : Introduction to Testing, Fault Modeling and Simulation]]>Week 10 : Test Pattern Generation, DFT and BISTWeek 11 : Low Power Design TechniquesWeek 12 : Low Power Design Techniques (contd.)
