Explore the world of Xvisor, an open-source type-1 monolithic hypervisor designed for embedded systems, in this 37-minute conference talk by Anup Patel from Western Digital. Delve into the RISC-V hypervisor extensions, Xvisor RISC-V internals, and the benefits of using Xvisor on RISC-V architecture, including memory footprint and overheads. Learn about the project's 8-year history, its mature and stable code base, and its support for ARM, RISC-V, and x86_64 architectures. Discover how Xvisor became the first open-source hypervisor successfully ported to RISC-V. Gain insights into key aspects such as VCPU context, host interrupts, context switching, guest MMIO emulation, RAM handling, SBI interface, device tree-based configuration, and zero-copy inter-guest transfer. Understand why Xvisor is ideal for embedded systems and explore its current state in the RISC-V ecosystem.
Overview
Syllabus
Western Digital
Roadmap
RISC-V H-Extension: Privilege Mode Changes
RISC-V H-Extension: CSR changes
RISC-V H-Extension Two-stage MMU
RISC-V H-Extension: I/O & Interrupts
What is Xvisor ?
Xvisor: Traditional Classification
Xvisor: Features (Contd.)
Xvisor: Key Aspects (Contd.)
Xvisor RISC-V: VCPU Context
Xvisor RISC-V: Host Interrupts
xvisor RISC-V: Context Switch
xvisor RISC-V: Guest MMIO Emulation
xvisor RISC-V: Guest RAM handling
Xvisor RISC-V: SBI Interface
xvisor RISC-V: Device tree based configuration
xvisor RISC-V: Zero-copy Inter-Guest Transfer
xvisor RISC-V: Code Size and Memory Usage
xvisor RISC-V: Ideal for Embedded Systems
xvisor RISC-V: Current State
Taught by
Linux Foundation
Tags
Related Courses
-
Computer Architecture with an Industrial RISC-V Core [RVfpga]
-
Developing the RISC-V Hypervisor Extensions in QEMU
-
Linux on RISC-V and the New OS-A Platform
-
AIA Virtualization in KVM RISC-V - Advanced Interrupt Architecture Overview
-
Base Porting of Linux Kernel on RISC-V Architecture
-
The Future of Linux on RISC-V
