Modular Hardware Design of Pipelined Circuits with Hazards

Explore a groundbreaking approach to modular hardware design for pipelined circuits with hazards in this 19-minute conference talk from PLDI 2024. Delve into the challenges of modularizing high-performance pipelined circuits with structural, data, and control hazards, and discover how the proposed "hazard interfaces" overcome these obstacles. Learn about the generalization of valid-ready interfaces and the implementation of combinators that facilitate control logic decomposition. Examine the development of a compiler and type checker for a prototype language supporting these new concepts. Gain insights from case studies on a 5-stage RISC-V CPU core and 100 Gbps Ethernet NIC, demonstrating the effectiveness of hazard interfaces in achieving modular design without compromising performance, power, or area compared to reference designs in Chisel and Verilog.