Masking in RISC-V Architecture - CHES 2024

Explore a comprehensive session on Masking techniques for RISC-V architecture presented at CHES 2024. Chaired by Markku-Juhani Saarinen, this 51-minute talk delves into the latest developments in side-channel attack countermeasures for RISC-V processors. Gain insights into cutting-edge research and practical applications of masking schemes designed to enhance the security of RISC-V implementations. Access additional resources, including research papers and presentation slides, through the official CHES 2024 program website for a deeper understanding of this critical topic in hardware security.