Overview
Syllabus
Intro
About Me #1
Why do we develop for RISC-V?
RISC-V Overview
RISC-V: Timers
RISC-V: code models
RISC-V: Kernel Assembly
RISC-V: our development platforms
RISC-V: Barebox on qemu
RISC-V Linux Header
RISC-V: Barebox on Beaglev
RISCV: HART(CPU) Bootup
Peripherals
A Primer on Cache Coherency
Cache-Coherent Interconnects
Device mastering the Bus
Linux DMA Mappings
DMA Mappings on ARM
Cache Coherency on RISC-V
Cache In-Coherency on RISC-V
Allwinner Dl (CPU: Alibaba Xuan Tie C906)
StarFive JH-7100 (CPU: SiFive U74)
Privilege Modes
trap-and-emulate
Supervisor Binary Interface
JH7100 Clock/Reset Handling
Got you interested?
Taught by
Linux Foundation