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Udemy

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

via Udemy

Overview

Using Xilinx Vivado Design Suite and Vitis 2020.2

What you'll learn:
  • Embedded System Design flow for Zynq AP SoC using Xilinx VITIS
  • Fundamentals strategies to use Xilinx Drivers
  • Development of C applications for Zynq Devices
  • Software Profiling with Vitis
  • Software and Hardware Debugging Strategies
  • Working with Interrupts

Xilinx Zynq SoC's are know to provide maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain. The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller, AXI Timers, GIC etc.

Taught by

Kumar Khandagle

Reviews

4.1 rating at Udemy based on 105 ratings

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