AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog

• ARM AXI Protocol
• Xilinx AXI Infrastructure
• Xilinx Vivado Tool
• FPGA and Verilog
• Zynq
• System Verilog

Why AXI?

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The answer is simple - there is NO any Socor complex system, which does not contain AXI. If your work somehow is connected with processor, controller or any other big system than there will be multiple AXI buses in the system. AXI bus is a ARM standard bus, which is supported by all hardware companies e.g. Xilinx, Intel, AMD and so on. And by the advance of AI the AXI is going to be more and more popular.

In this course AXI protocol and its sub-parts will be explained.

Also as a free side knowledge you will study Vivado with its IPs, simulation methods and many more.

Target Students

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The course is mainly targeted for FPGA designers, who are using AXI based modules in the design. Also the course will be useful for engineers who is starting to use AXI protocol.

The course is extremely helpful for graduate students who is looking for a new job as a FPGA or Soc Developer, in my previous 3 companies AXI questions were the most often to ask the fresh graduates for hire.

Course Content

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In the course mainly the basics of AXI protocol family is explained, which allows students easily understand and use AXI based IPs. This is more practical view of AXI usage allowing for jump start to use AXI based modules. The course does not go to FPGA board level,as the target is AXI protocol and Xilinx provided AXI Infrastucture understanding.The course concentrated on simulation level, not FPGA board running is done.

The AXI protocol is complex enough and sometimes it takes much time to get used to it. Usually the AXI protocol is easy to understand when you are familiar with much easy version of it, which are AXI-Stream and AXI-Lite. The course is based on bottom-up-style. At first I explain AXI-stream protocol, than explain AXI-Lite protocol in detail. We do both of these protocol designs using Verilog.

Than having all that baggage of knowledge we move to AXI protocol.

In the course I tried to review the ARM speck for AXI, hoping that this will help students easily jump in speck reading, after finishing the course.

Special Thanks:

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I want to express special thanks to Eduard Vardanyan, from ARM, for his great support in making this course. His profound experience and deep knowledge helped me to explain complex AXI parts simply. Without his help I could not do this.

Caution:

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Also I apologize for my English, I tried my best to speak clearly and grammatically correct, however sometimes there are some mistakes. I really hope that my non-native English will not bother students to understand the material.

Course Materials:

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All course codes can be downloaded from Github.

Note: If you have software background, I would suggest little bit become familiar with Verilog. There are several lectures which require Verilog and hardware basics.