Digital system design course focuses on design digital system from scratch. The course focuses on designing combinational and sequential building blocks, using these building blocks to design bigger digital systems. During this course we also learn how to use Verilog to design/model a digital system. INTENDED AUDIENCE :CSE, EE, ECE undergraduate studentsPREREQUISITES : NoneINDUSTRIES SUPPORT :Any VLSI related company: Intel, AMD, TI, nVIDIA, Qualcomm, etc.
Overview
Syllabus
Week 1:Introduction of digital systems. Number system
Week 2: Number representation: BCD, floating point numbersWeek 3:Boolean algebra, application of Boolean algebra in minimization of Boolean expressionsWeek 4:Boolean minimization using K-map and Quine McCluskey method. Introduction to VerilogWeek 5:MSI Logic: Multiplexer, encoder, decoderWeek 6:Arthimetic circuits: Adder, subtractor, multiplier, comparatorWeek 7:Latches and flipflop (SR, JK, T, D), countersWeek 8:Sequential logic like Registers, introduction to behavior modeling in VerilogWeek 9:Finite state machine, state graphs and tables.Week 10:Reduction of state table and state assignments. Arithmetic circuits using sequential design.Week 11: Register transfer level (RTL) design, RTL design examplesWeek 12:FPGA,VLSI design flow using HDL, introduction to behavior, logic and physical synthesis.
Week 2: Number representation: BCD, floating point numbersWeek 3:Boolean algebra, application of Boolean algebra in minimization of Boolean expressionsWeek 4:Boolean minimization using K-map and Quine McCluskey method. Introduction to VerilogWeek 5:MSI Logic: Multiplexer, encoder, decoderWeek 6:Arthimetic circuits: Adder, subtractor, multiplier, comparatorWeek 7:Latches and flipflop (SR, JK, T, D), countersWeek 8:Sequential logic like Registers, introduction to behavior modeling in VerilogWeek 9:Finite state machine, state graphs and tables.Week 10:Reduction of state table and state assignments. Arithmetic circuits using sequential design.Week 11: Register transfer level (RTL) design, RTL design examplesWeek 12:FPGA,VLSI design flow using HDL, introduction to behavior, logic and physical synthesis.
Taught by
S. Srinivasan
