Advanced Semiconductor Packaging

Overview

Throughout this course, you will be introduced to Pathway for Assembly and Packaging technologies for 7-nanometer silicon feature sizes and beyond. The course will present the evolution and impact of packaging on product performance and innovation. Specifically, we highlight how packaging has enabled better products via the use of heterogeneous integration by improving the interconnects for thermal management and signal integrity.

Syllabus

Welcome

Welcome to Advanced Packaging! Throughout this course, we will introduce you to Pathway for Assembly and Packaging technologies for 7-nanometer silicon feature sizes and beyond. We will present the evolution and impact of packaging on product performance and innovation. Specifically, we highlight how packaging has enabled better products via the use of heterogeneous integration by improving the interconnects for thermal management and signal integrity. Thank you for joining us & we hope you enjoy the materials!

Packaging Trends Part 1

In this module you will watch a lecture video by Ravi Mahajan who is an Intel Fellow and the Director of Pathfinding for Assembly and Packaging technologies for 7-nanometer (7nm) silicon and beyond in the Technology Development and Manufacturing Group at Intel Corporation. In this module Dr. Mahajan will discuss the evolution and impact of packaging on product performance and innovation. He shows how packaging has enabled better products using heterogeneous integration (HI) by improving the interconnects, signaling, power delivery and thermals over the years.

Packaging Trends Part 2

In this module Dr. Mahajan will discuss how advanced packaging technologies enable the integration of diverse components and functionalities into microelectronics systems. You will learn about the importance of advanced packaging for the future of computing and communication.

Heterogeneous Integration Part 1

In this module Dr. Mahajan will discuss how interconnect scaling can enable complex multi-chip packages (MCPs) that combine different types of chips and technologies. You will learn about the various interconnect options and trade-offs for MCPs, and how to blend 2D and 3D architectures.

Heterogeneous Integration Part 2

In this module Dr. Mahajan will discuss the trends in interconnect scaling for microelectronics systems. You will learn how 2D and 3D die-to-die (D2D) interconnects can enable high performance, how D2D link standardization can facilitate systematic and modular design of multi-chip packages (MCPs), and how co-packaging optics can address the challenge of off-package bandwidth scaling in future systems.

Advanced Packaging End of Course Summary

In conclusion of Advanced Packaging, we would like to summarize the main takeaways. Starting with Pathway for Assembly and Packaging technologies, we discussed trends in interconnect scaling of microelectronics systems 7-nanometer (7nm) silicon and beyond. During our presentations, we saw how 2D and 3D die-to-die (D2D) interconnects can enable high performance and can facilitate the systematic and modular design of multi-chip packages (MCPs). Turning to the future, we estimated how co-packaging optics could address the challenge of off-package bandwidth scaling in future systems.