Enabling Next-Generation Processor Simulations with SimEng - NHR PerfLab Seminar

Enabling Next-Generation Processor Simulations with SimEng - NHR PerfLab Seminar

NHR@FAU via YouTube Direct link

Funding

25 of 38

25 of 38

Funding

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Classroom Contents

Enabling Next-Generation Processor Simulations with SimEng - NHR PerfLab Seminar

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  1. 1 Introduction
  2. 2 Steves background
  3. 3 SimEng advantages
  4. 4 Asimov project
  5. 5 Ideal processor
  6. 6 Design space exploration
  7. 7 Design goals
  8. 8 Marvel Thunder X2
  9. 9 YAML files
  10. 10 Other models
  11. 11 Current work
  12. 12 HPC Benchmarks
  13. 13 Instruction Trace Viewer
  14. 14 Lark
  15. 15 Vector designs
  16. 16 Vector widths
  17. 17 Linear algebra kernels
  18. 18 DGM
  19. 19 Arm V1
  20. 20 Scalable Matrix Extension
  21. 21 A64FX Extension
  22. 22 Resnet
  23. 23 Future plans
  24. 24 Conclusions
  25. 25 Funding
  26. 26 Questions
  27. 27 Template magic
  28. 28 Simplicity
  29. 29 Configuration
  30. 30 Floating Point Operations
  31. 31 SimEng Code
  32. 32 Memory Traffic
  33. 33 Manual Work
  34. 34 Documentation
  35. 35 Reverse Engineering
  36. 36 Usability
  37. 37 Ease of use
  38. 38 Build a static binary

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