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Stanford University

Stanford Seminar - QED and Symbolic QED- Dramatic Improvements in SoC Validation and Debug

Stanford University via YouTube

Overview

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Explore a Stanford seminar on QED (Quick Error Detection) and Symbolic QED, focusing on dramatic improvements in System-on-Chip (SoC) validation and debugging. Delve into the challenges posed by increasing IC complexity and the critical importance of post-silicon validation. Learn about QED techniques, including Duplicate & Check, Diversity-Enhanced QED, and Proactive Load & Check, and their impact on improving coverage and error detection latency. Examine real-world applications of QED in Intel® Core™ i7 hardware, addressing difficult logic bugs and power management issues. Investigate the concept of Symbolic QED and its advantages over traditional Bounded Model Checking (BMC). Gain insights into bug localization techniques and the universal property of QED checks. Understand how these advanced methodologies contribute to more efficient and effective SoC validation processes in the face of escalating system-level complexities.

Syllabus

Introduction.
Staggering IC Complexity.
Post-Silicon Validation Critical.
Post-Silicon Validation Difficult.
Scalability Barriers.
Bigger Obstacles at System Level.
Bug Example.
QED Example: Duplicate & Check Validation program.
QED Example: Duplicate & Check QED Trace.
QED Improves Coverage.
Diversity-Enhanced QED.
QED: Proactive Load & Check.
QED Coverage Considerations.
Error Detection Latency vs. Intrusiveness Improved error detection latency.
Intel® Core™ i7 Hardware.
8-Core QED: Difficult Logic Bugs.
8-Core QED: Power Management Bugs 100%.
Hybrid QED: Logic Bug Results.
Bug Localization.
Symbolic Quick Error Detection.
Traditional Bounded Model Checking.
BOUNDED MODEL CHECKING (BMC).
Traditional BMC vs. Symbolic QED.
BMC Challenge (1): Property.
Universal Property: QED Check.
QED Module.
QED Guarantees Quick Detection.
Partial Instantiation.

Taught by

Stanford Online

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