Explore the innovative NVIDIA Denver processor and dynamic code optimization techniques in this Stanford seminar. Delve into the TEGRA K1 architecture with Dual Denver CPUs, examining pipeline skew, microarchitecture, and performance metrics. Contrast idealistic and cynical views of CPU design, and discover how dynamic code optimization (DCO) bridges hardware and software in microarchitecture. Analyze real-world code examples from benchmarks like 186.CRAFTY and 164.GZIP, and gain insights into historical binary translation systems. Learn about DCO's "optimize once, use many times" approach and its impact on CPU design simplifications.
Overview
Syllabus
Introduction.
TEGRA K1 with Dual Denver CPUs.
DENVER VALUE PROPOSITION.
PIPELINE SKEW.
SKEWED PIPELINE.
Pipeline Microarchitecture - Mispredict Penalty.
DENVER PERFORMANCE.
IDEALISTIC VIEW OF CPU DESIGN.
CYNICAL VIEW OF CPU DESIGN.
HW VS SW IN MICROARCHITECTURE.
DCO VIEW OF CPU DESIGN.
DCO UARCH SIMPLIFICATIONS.
DYNAMIC CODE OPTIMIZATION OPTIMIZE ONCE, USE MANY TIMES.
186.CRAFTY EXECUTION -3% of benchmark run.
CODE EXAMPLE FROM 164.GZIP.
HISTORICAL BT SYSTEMS.
Taught by
Stanford Online
