Explore Centaur Technology's groundbreaking microprocessor design in this Stanford seminar featuring Glenn Henry. Delve into the innovative x86 core and the industry's first integrated AI Coprocessor for x86 systems. Learn about the high-performance x86 microprocessor cores supporting the latest extensions and the clean-sheet AI Coprocessor designed for efficient deep-learning applications. Discover the proven scalable SoC platform with eight x86 cores and an AI Coprocessor capable of 20 trillion AI operations per second. Gain insights into the architecture's compact design, extensible platform, and impressive specifications. Understand the coprocessor's objectives, memory structure, hardware components, and implementation challenges. Examine the SimD and slice architectures, instruction memory, neural processing units, and benchmarking processes. Uncover the intricacies of this cutting-edge technology that combines x86 performance with dedicated AI processing capabilities.
Overview
Syllabus
Introduction
Centaur Technology
History
Why Coprocessor
Performance
Objectives
Art
Memory
Hardware
Rings
Die
Connectivity
ReadWrite
DMA Engines
Both Buses
SimD Architecture
Slice Architecture
Instruction Memory
RAM
Why is RAM not coherent
Neural Data Unit
Neural Processing Unit
Output Unit
Pipeline Above
Implementation Challenges
Code
Instructions
Software
Benchmarking
Benchmarks
Taught by
Stanford Online
