Explore the cutting-edge advancements in Machine Learning Recommendation acceleration through a Stanford seminar featuring Dave Ditzel, founder and executive Chairman of Esperanto Technologies Inc. Dive into the design of the 7nm ET-SoC-1 chip, which incorporates over a thousand low-power RISC-V processors and a distributed on-die memory system. Learn how Esperanto extended the RISC-V instruction set to achieve over 100 TOPS of performance while consuming less than 20 watts of power. Discover the challenges, approaches, and constraints in chip design, including energy efficiency, computing neighborhoods, grouping, and parallelization. Gain insights into the memory system, form factors, software considerations, vector operations, tensor multiplication, and integer operations. Examine benchmarks, the Maxion system, and the current state of development in this fascinating exploration of next-generation ML hardware.
Stanford Seminar - Accelerating ML Recommendation with Over a Thousand RISC-V-Tensor Processors
Stanford University via YouTube
Overview
Syllabus
Introduction
The Chip
Challenges
Different approaches
Constraints
Energy Efficiency
Computing Neighborhood
Grouping
Parallelization
More Details
Memory System
Other Form Factors
Software
Vector Operations
Tensor Multiply
Example
Integer Operations
Instructions
Benchmarks
Maxion
Summary
Where are we
First silicon
Taught by
Stanford Online
