Post-Moore Spatial Computing: From Chips to Clusters

Explore the challenges and solutions in post-Moore's law computing in this 38-minute conference talk by the Scalable Parallel Computing Lab at ETH Zurich. Delve into the complexities of scaling compute power for artificial intelligence as Moore's law ends. Examine the growing discrepancy between communication and computation in chiplets, chips, and wafers, and understand how Rent's rule limits off-chip bandwidth. Learn about the importance of spatial program layouts at all hierarchy levels and discover techniques for arranging dataflow graphs on chips and specialized system topologies. Gain insights into the future of high-performance computing and deep learning by understanding how to exploit algorithms' spatial nature through intelligent mapping to optimized physical compute devices. Acquire a toolbox of ideas to address these challenges across various levels, from microchips to entire clusters.