FLASH - Towards a High-performance Hardware Acceleration Architecture for Cross-silo Federated Learning

Explore a groundbreaking conference talk on FLASH, a high-performance hardware acceleration architecture designed for cross-silo federated learning systems. Delve into the innovative approach of extracting and implementing two basic operators—modular exponentiation and multiplication—as highly efficient engines to achieve adequate acceleration for nine widely-used cryptographic operations. Learn about the dataflow scheduling scheme that dynamically composes different cryptographic operations, maximizing resource utilization. Discover the impressive performance gains achieved by FLASH, including up to 14.0× and 3.4× acceleration over CPU and GPU respectively, and its integration with FATE, the most widely-adopted cross-silo FL framework. Gain insights into the potential of FLASH as an ASIC, offering a 23.6× performance improvement upon the FPGA prototype.