Overview
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Learn the fundamentals of VHDL (VHSIC Hardware Description Language) in this introductory lecture from the ECED2200 Digital Circuits course. Explore general concepts, software and hardware considerations, modules, continuous assignments, and main HDL characteristics. Dive into VHDL's syntax, including case sensitivity, white space usage, and control structures like if/case/loop statements. Examine entities, concurrent signal assignments, and various types of signal assignments. Understand processes, if statements, and state machines (Mealy and Moore). Access additional VHDL examples and resources available at Dalhousie University. Refer to the provided links for class details, source code, and a free VHDL book to supplement your learning.
Syllabus
Intro
GENERAL NOTES
SOFTWARE
HARDWARE
MODULES
CONTINUOUS ASSIGNMENTS
MAIN HDL'S
CASE SENSITIVITY
WHITE SPACE
IF/CASE/LOOP STATEMENTS
ENTITIES
CONCURRENT SIGNAL ASSIGNMENT
EXAMPLE 1
CONDITIONAL SIGNAL ASSIGNMENT
SELECTED SIGNAL ASSIGNMENT
PROCESSES
IF STATEMENTS
MEALY STATE MACHINE
MOORE STATE MACHINE
MORE VHDL EXAMPLES
RESOURCES AT DALHOUSIE
Taught by
Colin O'Flynn