Explore on-chip debug interfaces and hardware hacking techniques in this DerbyCon 3.0 conference talk. Delve into the world of JTAG architecture, TAP controllers, and UART protocols as Joe Grand presents the JTAGulator, a tool for assisted discovery of debug interfaces. Learn about hardware design requirements, PCB layouts, and component selection for building such devices. Witness demonstrations of IDCODE scans, BYPASS scans, and UART scans, while understanding potential limitations. Gain insights into manually determining pin functions and identifying external interfaces, all essential skills for hardware security professionals and enthusiasts.
Overview
Syllabus
Introduction
Goals
Inspiration
Identifying Interfaces: External
Manually Determining Pin Function
On-Chip Debug Interfaces
JTAG:Architecture
JTAG:TAP Controller
JTAG: Protection
JTAG: HW Tools
UART 3
Hardware
Design Requirements
Block Diagram
PCB
Propeller/Core 2
USB Interface
Adjustable Target Voltage
Level Translation
Input Protection
Bill-of-Materials
Source Tree
Propeller Resources
IDCODE Scan
BYPASS Scan
UART Scan
Scan Timing
Demonstration
Possible Limitations
A Poem
