Delivering 224G SerDes with a Path to 448G to Address AI/ML Bandwidth Demand

Learn about cutting-edge high-speed interconnect solutions in this 15-minute conference talk from Ciena's Senior Director of Analog ASIC, Naim Ben-Hamida. Explore the groundbreaking development of the industry's first 3nm DSP ASIC and single carrier 1.6Tb/s coherent solution. Gain detailed insights into the performance capabilities of 3nm-based 224G SerDes technology and understand the key factors driving the evolution towards 448G SerDes, including the critical role of higher analog bandwidth components. Watch a proof-of-concept demonstration that showcases how these advancements address the growing bandwidth demands of AI and machine learning applications.