CXL-Enabled Heterogeneous Active Memory Tiering: Architecture and Implementation

Watch a 17-minute conference talk from the Open Compute Project exploring CXL Type2-based disaggregated memory architecture that extends far memory capabilities to remote heterogeneous memory using standard high-speed ethernet. Learn how intelligence is required at every level of the disaggregated memory fabric, utilizing techniques like prefetching, caching, and near memory/storage compute to address high latency challenges in far memory access. Discover how the fabric memory controller (FPGA/ASIC) evaluates requesting agent needs, analyzes cluster-level telemetry, and manages data movement, placement, replication, and compression across the far memory hierarchy. Understand how this approach complements OS-based techniques for near and far memory movement, while enabling both memory tiering and pooling benefits through extended far memory tiers to remote nodes, ultimately providing enhanced capacity, bandwidth, and multi-node resource sharing capabilities.