Chiplet-based Reconfigurable Open Compute Accelerator Module Architecture and Platform

Learn about a modular chiplet-based platform design in this 15-minute technical talk from Distinguished Engineer Suresh Subramaniam. Explore how the Reconfigurable Open Compute Accelerator Module (ROAM) platform builds upon existing OAI infrastructure to enable advanced packaging and chiplet integration. Discover the System in Package (SiP) architecture featuring standardized footprints that accommodate up to 8 domain-specific accelerator chiplets, IO chiplets, and hub/bridge/switch chiplets. Understand how standardization of chiplet footprints promotes modularity, scalability, and innovation in domain-specific accelerator offerings through clear power, performance, and area specifications. Examine the potential for Plug and Play Chiplets (PnPC) and how high composability enables targeted microservices in this extension of previous OCP accelerator module discussions.