Explore the CHERI (Capability Hardware Enhanced RISC Instructions) architecture and its implementation in RISC-V processors in this informative talk from TASER 2021. Delve into hardware principles, software models, and implementations of CHERI, gaining insights into how this technology enhances security and mitigates exploitation paths. Learn about the fundamental concepts and practical applications of CHERI-RISC-V as presented by Simon Moore from the University of Cambridge.
CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge
Overview
Syllabus
Introduction
Hardware Principles
Software Models
Implementations
exploitation paths
wrap up
Taught by
TheIACR
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Computer Architecture with an Industrial RISC-V Core [RVfpga]
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CHERI - A Hybrid Capability-System Architecture for Scalable Software Compartmentalization
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Stanford Seminar - Thunderclap & CHERI - Capability Hardware-Enhanced RISC Instructions
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RISC-V Cryptography Extensions - Current Status and Future Plans
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Linux on Open Source Hardware with RISC-V
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TinyML Talks - State of Hardware & Software Ecosystem for Low-Power ML Applications on RISC-V
