The CPU Cache - Instruction Re-Ordering Made Obvious

Explore the intricacies of CPU cache and instruction reordering in this comprehensive 90-minute conference talk from CppNow. Delve into the fundamental principles of CPU cache architecture, its critical role in modern multi-core processors, and its impact on software performance. Examine how the CPU and compiler collaborate to reorder instructions, optimizing resource utilization while potentially complicating debugging processes. Gain insights into the C++ Standard's "As-If" rule and the additional tools provided by C++11, including the memory model, atomics, memory fences, and threading libraries. Investigate the anatomy of CPU cache, including registers, cache levels, cache lines, data bus, and instruction pipeline. Understand the compiler's responsibilities and the sophisticated techniques employed by processor cores at runtime. Develop a foundational understanding of CPU cache issues and terminology, essential for C and C++ programmers to leverage parallelism and address concurrency concerns effectively. Access accompanying slides for visual reference and further study.