Explore microarchitectural attacks on hardware RISC-V CPUs in this 14-minute IEEE conference talk. Delve into the research conducted by experts from CISPA Helmholtz Center for Information Security, including Lukas Gerlach, Daniel Weber, Ruiyi Zhang, and Michael Schwarz. Gain insights into the security risks associated with RISC-V architecture and understand the potential vulnerabilities that can be exploited through microarchitectural attacks. Learn about the implications of these findings for the future of RISC-V CPU design and cybersecurity measures.
A Security RISC - Microarchitectural Attacks on Hardware RISC-V CPUs
Overview
Syllabus
A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs
Taught by
IEEE Symposium on Security and Privacy
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