ABOUT THE COURSE:This course would deal with the circuit design techniques in low voltage regime, where the PVT variations are malfunctioning the circuit performance. The understanding of MOSFET or/and FinFET operation in weak inversion region, followed by development of robust circuit designing techniques in Digital, Analog and Mixed-signal designs. Objective: To understand essential aspects of low voltage operation of MOSFETs and CMOS circuits comprehensively and to learn to design such circuits.INTENDED AUDIENCE: Student interested in VLSI circuit design and device-circuit interaction.PREREQUISITES: Courses on digital logic design, digital VLSI and analog circuit design and basic MOS device physicsaxINDUSTRY SUPPORT: All VLSI Design companies (Cadence, Synopsys, Mentor Graphics, Texas Instruments, Micron etc.). Already, industry professionals who are students of IITR’s M.Tech (VLSI) program take this course as an elective.
Overview
Syllabus
Week 1:Lecture 1 : Introduction and MotivationModule 1 : MOSFET operation in weak and moderate inversion regions:Lecture 2 : Review of MOSFET operationLecture 3 : Review of MOSFET operationLecture 4 : Basic charge modelLecture 5 : Basic charge model
Week 2:Lecture 6 : Basic charge modelLecture 7 : Basic charge modelLecture 8 : Basic charge modelModule 2 : FINFET operation in weak and moderate inversion regions:Lecture 9 : Review of FinFET operationLecture 10 : Review of FinFET operation
Week 3:Lecture 11 : Basic charge modelLecture 12 : Basic charge modelLecture 13 : Basic charge modelModule 3 : MEP for low voltage operation and Transistor sizing for Near Threshold circuits:Lecture 14 : Minimum Energy Point (MEP)Lecture 15 : Transistor sizing for combinational circuits (Inverter)
Week 4:Lecture 16 : Transistor sizing for combinational circuits (Inverter)Lecture 17 : Transistor sizing for combinational circuits (Stacked gates)Lecture 18 : Transistor sizing for combinational circuits (Stacked gates)Lecture 19 : Transistor sizing for combinational circuits (Stacked gates)Lecture 20 : Multi-stage circuit sizing
Week 5:Lecture 21 : Multi-stage circuit sizingLecture 22 : Effective drive current models for NTV operationLecture 23 : Effective drive current models for NTV operationModule 4 : Sequential Circuits for Near-Threshold Voltage operations:Lecture 24 : Operation of sequential cells: Latch and FlipflopLecture 25 : Operation of sequential cells: Latch and Flipflop
Week 6:Lecture 26 : Warning Flip-Flop design and operationLecture 27 : Warning Flip-Flop design and operationLecture 28 : Warning Flip-Flop design and operationLecture 29 : PVT variation analysis in NTV circuitsLecture 30 : PVT variation analysis in NTV circuits
Week 7:Module 5 : Near-Threshold Voltage digital CMOS memory design:Lecture 31 : Introduction, Types of memory (SRAM/DRAM/NVM/ROM)Lecture 32 : SRAM read/write operationLecture 33 : SRAM 6T bit cell design (CR/PR)Lecture 34 : SRAM 6T bit cell design (CR/PR)Lecture 35 : Noise Margin (HSNM/RSNM/WSNM)
Week 8:Lecture 36 : Memory peripherals (Sense Amplifier & Pre-charge)Lecture 37 : Memory peripherals (Decoder/ Column-Mux/Drivers)Module 6 : Near-Threshold Voltage based special circuits:Lecture 38 : Resilient circuitsLecture 39 : Level shiftersLecture 40 : Level shifters
Week 2:Lecture 6 : Basic charge modelLecture 7 : Basic charge modelLecture 8 : Basic charge modelModule 2 : FINFET operation in weak and moderate inversion regions:Lecture 9 : Review of FinFET operationLecture 10 : Review of FinFET operation
Week 3:Lecture 11 : Basic charge modelLecture 12 : Basic charge modelLecture 13 : Basic charge modelModule 3 : MEP for low voltage operation and Transistor sizing for Near Threshold circuits:Lecture 14 : Minimum Energy Point (MEP)Lecture 15 : Transistor sizing for combinational circuits (Inverter)
Week 4:Lecture 16 : Transistor sizing for combinational circuits (Inverter)Lecture 17 : Transistor sizing for combinational circuits (Stacked gates)Lecture 18 : Transistor sizing for combinational circuits (Stacked gates)Lecture 19 : Transistor sizing for combinational circuits (Stacked gates)Lecture 20 : Multi-stage circuit sizing
Week 5:Lecture 21 : Multi-stage circuit sizingLecture 22 : Effective drive current models for NTV operationLecture 23 : Effective drive current models for NTV operationModule 4 : Sequential Circuits for Near-Threshold Voltage operations:Lecture 24 : Operation of sequential cells: Latch and FlipflopLecture 25 : Operation of sequential cells: Latch and Flipflop
Week 6:Lecture 26 : Warning Flip-Flop design and operationLecture 27 : Warning Flip-Flop design and operationLecture 28 : Warning Flip-Flop design and operationLecture 29 : PVT variation analysis in NTV circuitsLecture 30 : PVT variation analysis in NTV circuits
Week 7:Module 5 : Near-Threshold Voltage digital CMOS memory design:Lecture 31 : Introduction, Types of memory (SRAM/DRAM/NVM/ROM)Lecture 32 : SRAM read/write operationLecture 33 : SRAM 6T bit cell design (CR/PR)Lecture 34 : SRAM 6T bit cell design (CR/PR)Lecture 35 : Noise Margin (HSNM/RSNM/WSNM)
Week 8:Lecture 36 : Memory peripherals (Sense Amplifier & Pre-charge)Lecture 37 : Memory peripherals (Decoder/ Column-Mux/Drivers)Module 6 : Near-Threshold Voltage based special circuits:Lecture 38 : Resilient circuitsLecture 39 : Level shiftersLecture 40 : Level shifters
Taught by
Prof. Anand Bulusu
