Although FPGAs continue to grow in capacity, FPGA-based soft processors have grown little because of the difficulty of achieving higher performance in exchange for area. Superscalar out-of-order processor microarchitectures have been used successfully for hard processors for many years, but have so far been avoided for FPGAs due to the area increase and the expectation that a loss in clock frequency would more than offset the instructions-per-cycle (IPC) gains.
This talk summarizes my attempt at designing an out-of-order x86 CPU for FPGA. With careful microarchitectural choices and circuit design, I show that it is possible to build a complex microarchitecture on an FPGA, getting about 2.7x performance per clock and 0.8x clock frequency of Altera's Nios II/f single-issue in-order processor. This talk will cover a high-level overview of the microarchitecture and some of the interesting LUT-based circuits used in the processor.
