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AutoML: Hardware-Aware NAS
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Classroom Contents
Using AI to Design Energy-Efficient AI Accelerators for the Edge
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- 1 Intro
- 2 Next tiny ML Talks
- 3 Computing Hardware Has Been in Every Corner
- 4 Today's New Challenges
- 5 One Network Cannot work for All Platforms
- 6 Datasets/Applications, Hardware, and Neural Networks
- 7 Outline of Talk
- 8 AutoML: Neural Architecture Search (NAS)
- 9 AutoML: Differentiable Architecture Search
- 10 AutoML: Hardware-Aware NAS
- 11 AutoML: Network-FPGA Co-Design Using NAS
- 12 Two Paths from Cloud to Tiny ML
- 13 Motivation: Template Pool
- 14 Motivation: Heterogeneous ASICS
- 15 Problem Statement
- 16 ASICNAS Framework
- 17 ASICNAS: Controller and Selector
- 18 ASICNAS: Evaluator
- 19 Results: Design Space Exploration
- 20 Comparison Results on Multi-Dataset Workloads
- 21 Future Work: Network-CIM Co-Design to Resolve Memory Bot
- 22 Conclusion: Take Away (1)
- 23 Arm: The Software and Hardware Foundation for tiny
- 24 TinyML for all developers Dataset
- 25 Qeexo AutoML for.Embedded Al
