Programmable In-Memory Computing Accelerator with 100 SRAM IMC Macros

Programmable In-Memory Computing Accelerator with 100 SRAM IMC Macros

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Introduction

1 of 15

1 of 15

Introduction

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Programmable In-Memory Computing Accelerator with 100 SRAM IMC Macros

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  1. 1 Introduction
  2. 2 Outline
  3. 3 Background
  4. 4 IMC Macros
  5. 5 Challenges
  6. 6 Limitations
  7. 7 Architecture
  8. 8 PE Mapping
  9. 9 Measurement Comparison
  10. 10 Summary
  11. 11 Questions
  12. 12 Leakage
  13. 13 Accuracy
  14. 14 Future of IMC
  15. 15 Sponsors

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