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Classroom Contents
Stanford Seminar - Dataflow for Convergence of AI and HPC - GroqChip
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- 1 Introduction
- 2 Dennis Axe
- 3 Hardware Software Interface
- 4 Pipeline
- 5 Core Architecture
- 6 Superlane Architecture
- 7 DomainSpecific Architecture
- 8 Data Types
- 9 Communication and Computation
- 10 Energy Difference
- 11 Functional Control Units
- 12 Superlane
- 13 Vector Processor
- 14 Memory System
- 15 Switch Execution Module
- 16 System Architecture
- 17 Topology
- 18 Packaging
- 19 Network
- 20 Normal RDMA
- 21 Communication model
- 22 Synchronous communication
