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Pipeline Above
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Classroom Contents
Stanford Seminar - Centaur Technology's Deep Learning Coprocessor
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- 1 Introduction
- 2 Centaur Technology
- 3 History
- 4 Why Coprocessor
- 5 Performance
- 6 Objectives
- 7 Art
- 8 Memory
- 9 Hardware
- 10 Rings
- 11 Die
- 12 Connectivity
- 13 ReadWrite
- 14 DMA Engines
- 15 Both Buses
- 16 SimD Architecture
- 17 Slice Architecture
- 18 Instruction Memory
- 19 RAM
- 20 Why is RAM not coherent
- 21 Neural Data Unit
- 22 Neural Processing Unit
- 23 Output Unit
- 24 Pipeline Above
- 25 Implementation Challenges
- 26 Code
- 27 Instructions
- 28 Software
- 29 Benchmarking
- 30 Benchmarks
