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Intro
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Classroom Contents
Squeezing the Hardware to Make Performance Juice
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- 1 Intro
- 2 A Modern Processor
- 3 Processor Organization: Intel Nehalem+
- 4 Skylake Backend (sustained 4 uops/cycle)
- 5 Intel Top-Down Approach
- 6 Processor Behavior: Branch Prediction
- 7 Processor Behavior: ILP
- 8 Processor Behavior: Vector Units
- 9 Processor Behavior: Parallelization
- 10 Categories of Vector Instructions
- 11 Instruction Performance
- 12 Vectorization: Matrix Multiplication
- 13 Vectorization: Vector Normalization
- 14 Vectorization: AoS vs. SOA
- 15 Vectorization: N-Body Simulation
- 16 Vectorized strstr Illustrated
- 17 Vectorization: strstr
- 18 Vectorization: Sorted Set Intersection
- 19 Cache Structure, typical i5 (no L4 EDRAM)
- 20 Cache: Data Access Reordering
- 21 Cache: Tiling
- 22 Memory Bottleneck
