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Designing for Security
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Classroom Contents
Silicon - Security's New Layer
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- 1 Introduction
- 2 DEFCON
- 3 IOActive
- 4 Backdoors
- 5 Masks
- 6 Supply chain security
- 7 Threat taxonomy
- 8 Case studies
- 9 NDS
- 10 Nintendo vs Atari
- 11 Embedded Security
- 12 Smart Cities
- 13 Hardware Security
- 14 Hardware Labs
- 15 Root of Trust
- 16 Chip Anatomy
- 17 Attackers Toolbox
- 18 Blackbox Analysis
- 19 Glitch Attack
- 20 JTAG
- 21 Default passwords
- 22 Embedded world
- 23 Reactive Ion Etching
- 24 Chemical Bath
- 25 Polishing
- 26 Probe station
- 27 Intel chip architecture
- 28 We are not hacking
- 29 He loves chip hacking
- 30 AES Engine
- 31 Pro Mutation
- 32 Chip Tour
- 33 Flash Memory
- 34 Billion Gate Problem
- 35 Power Conduit
- 36 Designing for Security
- 37 Best Practices
- 38 KERS
- 39 Securing supply chain
- 40 Partner screening
- 41 Assurances
- 42 Trusted Foundry Program
- 43 Lack of Trust and Supply Chain
- 44 Robots
