The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration

The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration

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Monolithic Die Design To Silicon Stacking Implementation

12 of 13

12 of 13

Monolithic Die Design To Silicon Stacking Implementation

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The Challenges of Scaling Beyond Moore's Law - From Monolithic Dies to 3D Heterogeneous Integration

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  1. 1 Intro
  2. 2 Outline
  3. 3 Simply Following Moore's Law Alone is No Longer the Best Technical and Economical Path Forward
  4. 4 SIP/MCM vs. Heterogeneously Integrated Chiplet-Based Architectures The transition from system on a chip (SoC) to system in a package (SIP)
  5. 5 Heterogenous Integration Leverages Multiple Packaging Technologies
  6. 6 The Needs of IC and Systems Designers are Converging
  7. 7 Silicon Stacking The Next IC Packaging Paradigm Change is Here...
  8. 8 3D Packaging Versus Silicon Stacking (3DHI)
  9. 9 Multi-Chiplet 3D Flow Challenges
  10. 10 Top-Level Design Aggregation and Optimization
  11. 11 Standards and Co-Design Support
  12. 12 Monolithic Die Design To Silicon Stacking Implementation
  13. 13 Conclusion

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