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Instruction Set Architecture (ISA)
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Classroom Contents
Linux on RISC-V with Open Hardware
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- 1 Intro
- 2 RISC-V (virtual) meetups around the world
- 3 Open Source Hardware
- 4 Instruction Set Architecture (ISA)
- 5 What is different about RISC-V?
- 6 RISC-V Base Integer ISA
- 7 RISC-V Standard Extensions
- 8 RISC-V and Industry
- 9 Is RISC-V an Open Source processor?
- 10 RISC-V Privileged Architecture
- 11 RISC-V Boot Flow
- 12 What is OpenSBI?
- 13 UEFI Support
- 14 RISC-V in the Linux kernel
- 15 Linux distro: Fedora
- 16 Linux distro: Debian
- 17 SiFive Freedom Unleashed
- 18 Microchip PolarFire SoC
- 19 Microchip Icicle board
- 20 SAVVY-V board
- 21 Kendryte K210
- 22 SiFive Unmatched
- 23 Sipeed board with Allwinner SoC
- 24 Open source FPGA toolchains
- 25 Team Linux on Badge
- 26 Why design an SoC in Python?
- 27 Open Source ECP5 FPGA boards
- 28 Trustworthy self-hosted computer
