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Control and Status Registers (CSRs)
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Classroom Contents
Linux on RISC-V and the New OS-A Platform
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- 1 Intro
- 2 What is different about RISC-V?
- 3 RISC-V base integer registers
- 4 RISC-V Standard Extensions
- 5 RISC-V International
- 6 RISC-V Open Hours
- 7 RISC-V open source cores
- 8 RISC-V software ecosystem
- 9 RISC-V Privileged Architecture
- 10 Control and Status Registers (CSRs)
- 11 RISC-V Virtual Memory
- 12 What is a Hart?
- 13 Advanced Interrupt Architecture (AIA)
- 14 Supervisor Binary Interface (SBI)
- 15 SBI Extensions
- 16 Hypervisor extension
- 17 OpenSBI Generic Platform
- 18 UEFI Support
- 19 RISC-V Platform Specification
- 20 RISC-V ACPI Platform Specification
- 21 RISC-V emulation in QEMU
- 22 RISC-V in the Linux kernel
- 23 Linux 5.18
- 24 Upcoming Linux 6.0
- 25 Work in progress
- 26 Linux distro: Fedora
- 27 Linux distro: Ubuntu
- 28 OpenEmbedded and Yocto
- 29 BuildRoot
- 30 T-Head PTE format
- 31 Page-Based Memory Types extension
- 32 Svpbmt support in Linux
- 33 Cache Management Operations
- 34 CMO support in Linux
- 35 RISC-V Developer Boards
