Completed
Phases of a transaction
Class Central Classrooms beta
YouTube videos curated by Class Central.
Classroom Contents
Introduction to HyperBus Memory Devices
Automatically move to the next video in the Classroom when playback concludes
- 1 Intro
- 2 What's in the presentation?
- 3 What's HyperBus?
- 4 HyperBus Memory Devices
- 5 HyperRAM
- 6 Phases of a transaction
- 7 Communication Protocol
- 8 Command Address (CA) Bits
- 9 Write Programming Sequence
- 10 Address space overlays (ASOs)
- 11 Types of HyperBus Memory Controllers (HBMC)
- 12 MMIO capable controllers
- 13 Kernel support for HyperFlash
- 14 Writing a HBMC driver
- 15 hyperbus ops
- 16 Registering Device
- 17 Device Tree representation
- 18 Accessing from user space
- 19 HyperFlash and SPI
- 20 Comparison to traditional SPI flash protocol
- 21 XSPI compliant HyperFlash
- 22 Extending spl-mem for HyperFlash
- 23 Future Enhancements
- 24 References
