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FPGA IO Getting In and Getting Out
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Classroom Contents
FPGA Design for Embedded Systems
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- 1 FPGA Design for Embedded Systems - Course Overview
- 2 Programmable logic and FPGA design
- 3 A Brief History of Programmable Logic
- 4 CPLD Architecture
- 5 LUTs and FPGA Architecture
- 6 LUTs for Logic Design
- 7 FPGA Design for Embedded Systems - Designing Adders
- 8 FPGA Design for Embedded Systems - Designing Multipliers
- 9 FPGA Design Flow
- 10 Downloading Quartus Prime
- 11 Installing Quartus Prime
- 12 Introducing Quartus Prime
- 13 Create a design project in Quartus Prime
- 14 Create a design in Quartus Prime
- 15 Compile a Design
- 16 View the RTL
- 17 Timing Analysis with Time Quest I
- 18 Timing Analysis with Time Quest II
- 19 Simulate a design with ModelSim
- 20 Many types of FPGAs
- 21 Xilinx CPLD Architecture
- 22 Xilinx Small FPGAs
- 23 Xilinx Large FPGAs
- 24 Altera CPLDs and Small FPGAs
- 25 Altera Large FPGAs
- 26 Microsemi Single chip FPGA solutions
- 27 Lattice Single Chip FPGA solutions
- 28 FPGA Design Expertise
- 29 Advanced Schematic Entry for FPGA Design Drawing and Hierarchy
- 30 Improving Productivity with IP Blocks
- 31 Improving Timing with Pipelining
- 32 FPGA IO Getting In and Getting Out
- 33 Pin Assignments Making them Spot On!
- 34 Programming the FPGA
- 35 Becoming one with Q Qsys System Design
- 36 Becoming one with Q Part II Qsys System Design Finishing Touches
- 37 Becoming one with Q Part III Qsys System Design Finishing Touches
