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Classroom Contents
Inter VM Data Exfiltration - The Art of Cache Timing Covert Channel on x86 Multi-Core
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- 1 Intro
- 2 Cache Timing Covert Channel
- 3 Disclaimer
- 4 The problem
- 5 I was caught
- 6 I did a video
- 7 Outline of the talk
- 8 Shared resources
- 9 Multiple socket
- 10 Cache line
- 11 Cache timing modulation
- 12 Demo
- 13 Test Program
- 14 Test Results
- 15 BIOS Prefetcher
- 16 Solution
- 17 Userspace
- 18 Physical Address
- 19 KSM
- 20 No synchronization primitive
- 21 Phase lock loop
- 22 CLflush
- 23 The Client
- 24 Monotonic Pulse
- 25 Timers
- 26 Jitter
- 27 Compensation
- 28 Results
- 29 Synchronization
- 30 Recap
- 31 Original experiment
- 32 CPU usage
- 33 Reverse shell example
- 34 Forward error correction
- 35 ReedSolomon
- 36 Reverse Shell
- 37 Disable KSM
- 38 Disable CL Flourish
- 39 Where Counters
- 40 Heuristic
