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Mealy and Moore State Machines (Part 2)
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Classroom Contents
Digital Electronics
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- 1 What is Signal?
- 2 What is an Analog Signal?
- 3 What is Digital Signal?
- 4 Need of Digital Signals
- 5 Introduction to Digital Electronics
- 6 Switch and Bits Intuition
- 7 Introduction to Boolean Algebra (Part 1)
- 8 Introduction to Boolean Algebra (Part 2)
- 9 Boolean Algebra Examples (Part 1)
- 10 Boolean Algebra Examples (Part 2)
- 11 Redundancy Theorem (Boolean Algebra Trick)
- 12 Sum of Products (Part 1) | SOP Form
- 13 Sum of Products (Part 2) | SOP Form
- 14 Product of Sums (Part 1) | POS Form
- 15 Product of Sums (Part 2) | POS Form
- 16 SOP and POS Form Examples
- 17 Minimal to Canonical Form Conversion (Part 1)
- 18 Minimal to Canonical Form Conversion (Part 2)
- 19 Examples & Tricks (SOP and POS Forms)
- 20 Positive and Negative Logic
- 21 Dual Form
- 22 Self Dual
- 23 Complement Meaning and Examples
- 24 Venn Diagram
- 25 Switching Circuits (Part 1)
- 26 Switching Circuits (Part 2)
- 27 Statement Problems in Boolean Algebra (Part 1)
- 28 Statement Problems in Boolean Algebra (Part 2)
- 29 Introduction to Number Systems
- 30 Binary Number System
- 31 Decimal to Binary Conversion
- 32 Decimal to Octal Conversion
- 33 Decimal to Hexadecimal Conversion
- 34 Binary to Decimal Conversion
- 35 Octal to Decimal Conversion
- 36 Hexadecimal to Decimal Conversion
- 37 Octal to Binary & Binary to Octal Conversion
- 38 Hexadecimal to Binary & Binary to Hexadecimal Conversion
- 39 Hexadecimal to Octal & Octal to Hexadecimal Conversion
- 40 Binary Addition
- 41 Binary Subtraction
- 42 Binary Multiplication
- 43 Binary Division
- 44 Octal Addition
- 45 Octal Subtraction
- 46 Octal Multiplication
- 47 Hexadecimal Addition
- 48 Hexadecimal Subtraction
- 49 Hexadecimal Multiplication
- 50 r's Complement
- 51 (r-1)'s Complement
- 52 1's and 2's Complement
- 53 Shortcut for 2's Complement
- 54 Data Representation using Signed Magnitude
- 55 Data Representation using 1's Complement
- 56 Data Representation using 2's Complement
- 57 Binary Subtraction using 1's Complement
- 58 Binary Subtraction using 2's Complement
- 59 Classification of Codes
- 60 Binary Coded Decimal (BCD) Code
- 61 BCD Addition
- 62 Shift Add 3 Method | Simple method for Binary to BCD conversion
- 63 2421 Code
- 64 Excess-3 Code (XS-3 Code)
- 65 Excess-3 Code Addition
- 66 Introduction to Gray Code
- 67 Binary to Gray Code Conversion
- 68 Gray Code to Binary Conversion
- 69 What is Parity?
- 70 Hamming Code | Error detection
- 71 Hamming Code | Error Correction
- 72 Logic Gates (Part 1)
- 73 Logic Gates (Part 2)
- 74 Logic Gates (Part 3)
- 75 Logic Gates (Part 4)
- 76 Logic Gates (Part 5) | Important!
- 77 Logic Gates (Part 6) | Important!
- 78 NAND Gate as Universal Gate (Part 1)
- 79 NAND Gate as Universal Gate (Part 2)
- 80 NOR Gate as Universal Gate
- 81 Karnaugh Map (K' Map) - Part 1
- 82 Karnaugh Map (K' Map) - Part 2
- 83 Karnaugh Map (K' Map) - Part 3
- 84 K' Map and Implicants
- 85 4 Variable Karnaugh Map (Part 1)
- 86 4 Variable Karnaugh Map (Part 2)
- 87 4 Variable Karnaugh Map (Part 3)
- 88 Don't Care in Karnaugh Map (K' Map)
- 89 Don't Care in K' Map (Response to Doubt)
- 90 K' Map using Max Terms (Part 1)
- 91 K' Map using Max Terms (Part 2)
- 92 5 variables K' Map
- 93 Quine-McCluskey Minimization Technique (Tabular Method)
- 94 Digital Electronics Previous Year Solution of DRDO & ISRO (Part 2)
- 95 Digital Electronics Previous Year Solution of DRDO & ISRO (Part 3)
- 96 4-Bit Even Parity Generator
- 97 Seven Segment Display Decoder
- 98 Seven Segment Display Decoder (Part 2)
- 99 Seven Segment Display Decoder (Part 3)
- 100 Comparison between Combinational and Sequential Circuits
- 101 Half Adder
- 102 Full Adder
- 103 Full Adder using Half Adder
- 104 4 Bit Parallel Adder using Full Adders
- 105 Half Subtractor
- 106 Full Subtractor | Easy Explanation
- 107 Realizing Half Adder using NAND Gates only
- 108 Realizing Half Adder using NOR Gates only
- 109 Realizing Full Adder using NAND Gates only
- 110 Realizing Half Subtractor using NAND Gates only
- 111 Realizing Half Subtractor using NOR Gates only
- 112 Realizing Full Subtractor using NAND Gates only (Part 1)
- 113 Realizing Full Subtractor using NAND Gates only (Part 2)
- 114 2-Bit Multiplier Using Half Adders
- 115 Carry Lookahead Adder (Part 1) | CLA Generator
- 116 Carry Lookahead Adder (Part 2) | CLA Adder
- 117 BCD Adder | Simple Explanation
- 118 Introduction to Multiplexers | MUX Basic
- 119 4X1 Multiplexer
- 120 8X1 Multiplexer
- 121 MUX Tree Basic | 4X1 MUX using 2X1 MUX | Easy Explanation
- 122 Implementing 8X1 MUX using 2X1 MUX
- 123 Implementing 8X1 MUX using 4X1 MUX (Special Case)
- 124 32X1 MUX using 8X1 MUX
- 125 Implementation of Boolean Function using Multiplexers
- 126 1-Bit Full Adder using Multiplexer
- 127 Logical Expression from Multiplexer
- 128 Introduction to Demultiplexer | 1:2 DEMUX
- 129 1:4 Demultiplexer
- 130 Full Subtractor using 1:8 Demultiplexer
- 131 Demultiplexer as Decoder
- 132 2-Bit Comparator
- 133 Introduction to Encoders and Decoders
- 134 Priority Encoder
- 135 Decimal to BCD Encoder
- 136 Octal to Binary Encoder
- 137 Hexadecimal to Binary Encoder
- 138 Full Adder Implementation using Decoder
- 139 Practice Problems on Combinational Circuits (Part 1)
- 140 Practice Problems on Combinational Circuits (Part 2)
- 141 Practice Problems on Combinational Circuits (Part 3)
- 142 Practice Problems on Combinational Circuits (Part 4)
- 143 Digital Electronics Test-1
- 144 Introduction to Sequential Circuits | Important
- 145 SR Latch | NOR and NAND SR Latch
- 146 What is a Clock?
- 147 Triggering Methods in Flip Flops
- 148 How to get Edge Triggering | Simulation using Multisim
- 149 Difference between Latch and Flip Flop
- 150 Introduction to SR Flip Flop
- 151 Truth Table, Characteristic Table and Excitation Table for SR Flip Flop
- 152 Introduction to D flip flop
- 153 Truth Table, Characteristic Table and Excitation Table for D Flip Flop
- 154 Introduction to JK flip flop
- 155 Truth Table, Characteristic Table and Excitation Table for JK flip flop
- 156 Race Around Condition or Racing in JK Flip Flop
- 157 Master Slave JK Flip Flop
- 158 Behaviour of Master Slave D Flip Flop
- 159 Introduction to T flip flop
- 160 Truth Table, Characteristic Table and Excitation Table for T flip flop
- 161 5 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion
- 162 T Flip Flop to D Flip Flop Conversion
- 163 SR Flip Flop to JK Flip Flop Conversion
- 164 SR Flip Flop to T Flip Flop Conversion
- 165 Preset and Clear Inputs in Flip Flop
- 166 Introduction to State Table, State Diagram & State Equation
- 167 Design Procedure for Clocked Sequential Circuits
- 168 Mealy and Moore State Machines (Part 1)
- 169 Mealy and Moore State Machines (Part 2)
- 170 Analysis of Clocked Sequential Circuits (with D Flip Flop)
- 171 Analysis of Clocked Sequential Circuits (with JK Flip Flop)
- 172 Analysis of Clocked Sequential Circuits (with T Flip Flop)
- 173 Sequence or Pattern Detector
- 174 Sequence Detector (Example)
- 175 State Reduction and Assignment
- 176 ASM Chart
- 177 ASM Chart for Moore State Machine
- 178 Difference between Synchronous and Asynchronous Sequential Circuits
- 179 Introduction to Counters | Important
- 180 Types of Counters | Comparison between Ripple and Synchronous counters
- 181 3 Bit Asynchronous Up Counter
- 182 4 Bit Asynchronous Up Counter
- 183 3 bit & 4 bit Asynchronous Down Counter
- 184 3 Bit & 4 Bit UP/DOWN Ripple Counter
- 185 Modulus of the Counter & Counting up to Particular Value
- 186 State Diagram of a Counter
- 187 Decade (BCD) Ripple Counter
- 188 How to Design Synchronous Counters | 2-Bit Synchronous Up Counter
- 189 3-Bit Synchronous Up Counter
- 190 3-Bit & 4-bit Up/Down Synchronous Counter
- 191 Ring Counter
- 192 Johnson's Counter (Twisted/Switch Tail Ring Counter)
- 193 Introduction to Registers
- 194 Data Formats and Classification of Registers
- 195 Shift Register (SISO Mode)
- 196 Shift Register (SIPO & PIPO Mode)
- 197 Shift Register (PISO Mode)
- 198 Bidirectional Shift Register
- 199 Universal Shift Register
- 200 Practice Problems on Sequential Circuits (Part 2)
- 201 Practice Problems on Sequential Circuits (Part 3)
- 202 Programmable Logic Array (PLA) | Easy Explanation
- 203 Programmable Array Logic (PAL)