Control of Transmon Qubits Using a Cryogenic CMOS Integrated Circuit

Control of Transmon Qubits Using a Cryogenic CMOS Integrated Circuit

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Block Diagram

10 of 19

10 of 19

Block Diagram

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Control of Transmon Qubits Using a Cryogenic CMOS Integrated Circuit

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  1. 1 Intro
  2. 2 Outline
  3. 3 Driven Transmon ("Lab Frame")
  4. 4 Tradeoff Between Coherence Time & Gate Duration Gate time avoid
  5. 5 Typical Single Qubit Control/Measurement Hardware
  6. 6 Brute Force Scaling: 54 Qubits
  7. 7 Brute Force Scaling: 138,240 Qubits
  8. 8 Cryo-CMOS XY Controller Specifications Key design challenges: (1) No device models for 3K (2) dissipation
  9. 9 Waveform Generation Approach
  10. 10 Block Diagram
  11. 11 Vector Modulator
  12. 12 Example Room Temperature Measurements
  13. 13 Integration into Quantum System for Experiments
  14. 14 Waveforms at Monitor Port
  15. 15 Feedthrough Cancellation
  16. 16 Rabi Experiment (22ns Pulse)
  17. 17 Coherence Time Measurements
  18. 18 Comparison w/state of the art
  19. 19 Summary • Fault tolerant quantum computers will require scalable control

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