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L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture
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Computer Organization and Architecture
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- 1 L-1.1: Computer Organization and Architecture Syllabus Discussion for GATE and UGC NTA NET
- 2 L-1.2: Von Neumann's Architecture | Stored Memory Concept in Computer Architecture
- 3 L-1.3:Various General Purpose Registers in Computer Organization and Architecture
- 4 L-1.4:Types of Buses (Address, Data and Control) in Computer Organization and Architecture
- 5 L-1.5: Common bus system using multiplexer | Computer organization and Architecture
- 6 L-1.6: Common Bus system| How basic computer works
- 7 L-1.7: Types of Instructions in General Purpose Computer | Computer Organization and Architecture
- 8 L-1.8: Data Transfer Instructions in Computer Organisation and Architecture
- 9 L-1.9: Arithmetic Instructions(Data Manipulation) in Computer Organisation and Architecture
- 10 L-1.10: Logical Instructions(Data Manipulation) in Computer Organisation and Architecture
- 11 L-1.11: Shift Instructions(Data Manipulation) in Computer Organisation and Architecture
- 12 L-1.12: Program Control Instructions(Types of Control Instructions) | Computer Organization
- 13 L-1.13: What is Instruction Format | Understand Computer Organisation with Simple Story
- 14 L-1.14: Question on Instruction Format | Computer Organization | UGC NTA NET June 2021
- 15 L-1.15: Single Accumulator CPU Organisation | Single Address Instructions in Computer Organisation
- 16 L-1.16: General Register CPU Organisation | Two and Three Address Instructions | COA
- 17 L-1.17: Register Stack Organisation | Zero Address Instructions | COA
- 18 L-1.18:Memory Stack Organisation | Memory stack Vs Register stack | COA
- 19 L-2.1: What is Addressing Mode | Various Types of Addressing Modes | COA
- 20 L-2.2: Implied Addressing Mode | Computer Organisation and Architecture
- 21 L-2.3: Immediate Addressing Mode | Computer Organisation and Architecture
- 22 L-2.4: Register Mode | Addressing Mode | Computer Organisation and Architecture
- 23 L-2.5: Register Indirect Mode | Addressing Modes | Computer Organisation and Architecture
- 24 L-2.6: Auto Increment and Decrement Addressing Modes | Computer Organisation and Architecture
- 25 L-2.7: Direct Addressing Mode || Computer Organisation and Architecture
- 26 L-2.8: Indirect Addressing Mode | Computer Organisation and Architecture
- 27 L-2.9: Relative Addressing Mode || Computer Organisation and Architecture
- 28 L-2.10: Base Register Addressing Mode || Computer Organisation and Architecture
- 29 L-2.11: Indexed Addressing Mode || Computer Organisation and Architecture
- 30 L-2.12: Question on Addressing Modes | Computer Organization | UGC NTA NET 2021
- 31 L-3.1: Memory Hierarchy in Computer Architecture | Access time, Speed, Size, Cost | All Imp Points
- 32 L-3.2: Independent vs Hierarchical Memory Organisation | 2-Level Memory Organisation
- 33 L-3.3: 3-Level Memory Organisation || Computer Organisation and Architecture
- 34 L-3.4: GATE 2004 Question on 3-Level Memory Organisation || Computer Organisation and Architecture
- 35 L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture
- 36 L-3.6: Direct Mapping with Example in Hindi | Cache Mapping | Computer Organisation and Architecture
- 37 L-3.7: GATE 2005 Question on Direct Mapping | Cache Mapping Questions | Computer Organisation
- 38 L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation
- 39 L-3.9: Advantages and Disadvantages of Direct Mapping | Cache Mapping | Computer Organisation
- 40 L-3.10: Set Associative Mapping with Examples in Hindi | Cache Mapping | Computer Organisation
- 41 L-3.11: Locality of Reference in Cache Memory | Spatial Vs Temporal Locality | Computer Organisation
- 42 L-3.12: Cache Replacement Algorithms in Computer Organisation and Architecture
- 43 L-3.13: LRU (Least Recently Used) Cache Replacement Algorithm | Computer Organisation & Architecture
- 44 L-3.14: Gate 2014 Question on Set Associative Cache Mapping | Computer Organisation and Architecture
- 45 L-3.15: FIFO Cache Replacement Policy with example | Computer Organisation and Architecture
- 46 L-3.16: LRU(least recently used ) Cache Replacement Policy | Computer Organisation and Architecture
- 47 L-4.1: Pipelining with real life example| Need of Pipelining | COA
- 48 L-4.2: Pipelining Introduction and structure | Computer Organisation
- 49 L-4.3: Pipelining Vs Non-Pipelining | Instruction Execution | Speedup, Efficiency, Utilization | COA
- 50 L-4.4: Stage Delay in Pipeline | Previous Year GATE Question | Computer Organisation & Architecture
- 51 L-4.5: Numerical Question on Pipelining | Previous year GATE Question | COA
- 52 L-4.6: What is Hazard in Pipelining | various types of Hazards | computer Architecture
- 53 L-4.7: Structural Hazards in Pipelining | Types of Hazards with Example in Hindi
- 54 L-4.8: Control Hazards in Pipelining | Types of Hazards with Example in Hindi
- 55 L-4.9: What is Read After Write(RAW) Hazards| Data Hazard in Pipelining with Example in Hindi | COA
- 56 L-4.10: Write After Read Hazard with Example|Data Hazards| Computer Organisation and Architecture
- 57 L-4.11: Write After Write Hazard | Data Hazards in Pipelining | Computer Organization &&Architecture
- 58 I/O Interface in Computer Organization
- 59 Daisy Chaining in Priority Interrupt | Priority Based Interrupt in I/O Organization
- 60 Parallel priority interrupt | I/O organization
- 61 Question on Interrupt Handling(I/O organization) | Computer Organization | UGC NTA NET June 2021
- 62 Question on DMA (Direct Memory Access) | Input/Output Organization| COA | UGC NTA NET June 2021
- 63 RISC vs CISC | Computer Organization & Architecture
