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Measuring Timing Side Channel
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Classroom Contents
Breaking Kernel Address Space Layout Randomization - KASLR - With Intel TSX
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- 1 Intro
- 2 Example: Linux
- 3 Example: town. OS X 10.10.5 Kernel Privilege Escalation Vulnerability
- 4 Kernel Address Space Layout Randomization (KASLR)
- 5 TLB Timing Side Channel
- 6 TSX Gives Better Precision on Timing Attack
- 7 Transactional Synchronization Extension
- 8 Abort Handler Suppresses Exceptions
- 9 Reducing Noise with Intel TSX
- 10 Measuring Timing Side Channel
- 11 Demo 2: Full Attack on Linux
- 12 Attack on Windows
- 13 Attack on OS X
- 14 Attack on Amazon EC2
- 15 Result Summary
- 16 Timing Side Channel (M/U)
- 17 Path for a mapped Page
- 18 Intel Cache Architecture
- 19 Path for an Executable Page
- 20 Path for a non-executable, but mapped Page
- 21 Cache Coherence and TLB
- 22 Discussions: Controlling Noise
- 23 Discussions: Countermeasures?
- 24 Conclusion
- 25 Any Question?
